About Eridan

Eridan connects the robots powering the physical AI era. It's how we're delivering on our mission: connect the planet to empower a sustainable, shared future. Our patented transmitter delivers the fast, reliable wireless that robots depend on, while transforming the economics of connectivity, slashing cost and energy footprint by 10x at global scale. Beyond robotics, our private 5G networks serve campuses, cities, industry and defense. From our headquarters in Sunnyvale to our office in Zagreb, we're a team that owns our work, speaks candidly, and moves with focus and urgency. Learn more about our mission here .

About this Job

We are seeking a Mid-Level FPGA Engineer to join our team and contribute to the development and evolution of our Open RAN Radio Unit (RU) platform. This role is ideal for someone who combines solid FPGA expertise with a strong understanding of digital signal processing and compute architectures, particularly in AI-driven systems.

Responsibilities

Design, develop, and integrate FPGA-based solutions for Open RAN Radio Units.
Implement and optimize digital signal processing (DSP) algorithms for high-performance compute applications.
Work with Xilinx (AMD) FPGA technologies, including Zynq-based platforms; Versal experience is a plus.
Integrate and validate designs using Vivado, ensuring timing closure, proper routing, and backend implementation correctness.
Collaborate with system and software teams to translate algorithmic requirements into efficient hardware implementations.
Contribute to feature development and enhancements of existing ORAN RU products.
Participate in board bring-up, debugging, and hardware validation processes.
Analyze and troubleshoot performance bottlenecks across FPGA and system-level designs.

Requirements

3–6 years of experience in FPGA design and development.
Strong understanding of digital signal processing (DSP) concepts and their hardware implementation.
Solid knowledge of compute architectures and interest in AI/ML acceleration on FPGA.
Hands-on experience with Xilinx (AMD) tools and platforms, especially Vivado and Zynq.
Experience with good digital design principles and practices for RTL design (VHDL/Verilog/SystemVerilog) and simulation workflows.
Familiarity with timing closure, synthesis, and place-and-route processes.
Comfortable working with hardware debugging tools and board bring-up procedures.
Experience with Siemens Questa simulation tools.
Experience with Git, GitHub and general principles of Continuous Integration process.
Experience with scripting and Linux environments.

Nice to Have

Experience with Xilinx Versal platforms.
Background in telecommunications systems.
Familiarity with Open RAN architecture and related protocols.
Experience with high-speed interfaces and data movement (e.g., Ethernet, PTP, SyncE JESD204).

Perks of working at Eridan

Work on new technology that will make a significant impact on global infrastructure
Ability to learn, develop, and advance within a flexible environment
Collaborate with smart, passionate, and helpful co-workers
Celebrate progress company-wide

Salary Range

Given our anticipated growth, we are open to hiring individuals with varying levels of experience to fill this role. Salary will be commensurate with job-related skills, experience and other relevant factors. The salary range for this role is between €3,500 and €4,300 plus benefits.

Eridan is an equal opportunity employer. We value and celebrate diversity and are committed to creating an inclusive environment for all employees. Qualified applicants will be considered for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.